The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a dummy pattern.
In semiconductor integrated circuit devices, it is generally practiced to provide a multilayer interconnection structure on a substrate formed with minute active devices, for interconnecting these active devices electrically.
A multilayer interconnection structure is formed of lamination of interlayer insulation films, wherein each of the interlayer insulation film is embedded with a corresponding interconnection pattern. Further, the interconnection patterns of different interlayer insulation films are connected with each other via via-holes formed in the interlayer insulation films to form a desired circuit.
In modern ultrafine semiconductor devices, there are formed huge number of active devices on the substrate as a result of increased integration density, and because of this, there are formed extremely complex interconnection patterns in the multilayer interconnection structure in many layers.
Thus, at the time of fabricating such a semiconductor integrated circuit having extremely complex interconnection patterns, it is generally inevitable that there occur some defects in the multilayer interconnection structure due to the failure of layout or defective fabrication process.
Thus, in order to produce such semiconductor integrated circuits of large integration density with high yield, it is essential to analyze the semiconductor integrated circuits that turned out to be defective.
Conventionally, analysis of the defective semiconductor integrated circuit device has been achieved by using an optical microscope such as a laser microscope having a large focal depth for detection of the interconnection patterns embedded in the multilayer interconnection structure. On the other hand, for the purpose of repair of defective parts, which may include formation of contact holes, disconnection of interconnection pattern, formation of contact pads for testing, or the like, it has been practiced to use a FIB (focused-ion-beam) processing apparatus or a scanning electron microscope that includes therein such FIB processing apparatus.
Thus, conventionally, it has been practiced to locate the defects in the multilayer interconnection by means of an optical microscope and conduct various repair works at that location by the FIB processing apparatus, such as formation of contact holes, disconnection of the interconnection patterns, formation of test contact pads, in correspondence to the defects thus detected. Here, it should be noted that an optical microscope can observe the lower interconnection patterns embedded in the multilayer interconnection structure, while an FIB processing apparatus or scanning electron microscopes can only observe the pattern shape at the outermost surface.
Meanwhile, in the semiconductor integrated circuit that uses a multilayer interconnection structure, it is practiced to secure planar surface for the interlayer insulation films by forming, in each of the interlayer insulation films, dummy patterns in correspondence to the regions where the interconnection patterns are sparsely distributed.
Thus, it has been practiced conventionally that, in the event a defect has been detected by the microscopic observation, the distribution of the dummy patterns in the vicinity of the detected defect is acquired at the same time. Thereby, the FIB processing apparatus identifies the location of the defect that has been detected by the optical microscope based on the distribution of the dummy patterns thus acquired and applies the necessary repair work at this location.
Further, Japanese Laid-Open Patent Application 9-306910 describes the technology of forming a specific dummy pattern that can be used as a mark in the dummy patterns with a uniform interval for facilitating the identification of the defect location by the FIB apparatus.
According to the technology disclosed in the foregoing Japanese Laid-Open Patent Application 9-306910, it becomes possible to locate the predetermined defect easily by using the FIB processing apparatus by carrying out a search while using such marks as the reference.
FIG. 1 shows the state of the interconnection pattern in a multilayer interconnection structure obtained by a laser microscope.
Referring to FIG. 1, it becomes possible to observe, as a result of use of the laser microscope, not only the uppermost interconnection pattern 11 in the multilayer interconnection structure but also the interconnection pattern 12 provided underneath the interconnection pattern 11. Thereby, it becomes possible to detect the disconnection or short circuit in the multilayer interconnection structure carrying out the circuit analysis operation based on the microscopic observation. Further, it can be seen that there is formed a large number of dummy patterns 11A in the multilayer interconnection structure at the same level as the uppermost interconnection pattern 11.
Contrary to this, FIG. 2 shows the pattern obtained for the case the surface of the same multilayer interconnection structure is observed by an FIB processing apparatus.
Referring to FIG. 2, it can be seen that, while the uppermost interconnection pattern 11 and the dummy patterns 11A are observable in this case, it is not possible to observe the interconnection pattern 12 underneath the interconnection pattern 11.
Now, in the case the dummy patterns 11A are distributed at random as shown in FIGS. 1 and 2, it is not difficult to identify the processing region circled in FIG. 1 in the FIB image of FIG. 2 from the distribution of the dummy patterns 11A.
However, in advanced ultrafine semiconductor integrated circuits, there occurs increase of density of the interconnection patterns with increase of the integration density, and associated therewith, there occurs an increase in the density of the dummy patterns that are formed in the region in which the interconnection patterns are formed sparsely. As a result of this, there arises a situation in which the dummy patterns 11A are repeated regularly as represented in FIG. 3.
It should be noted that, in the situation in which the dummy patterns 11A are repeated regularly as shown in FIG. 3, it is difficult to locate the region circled in the drawing, in which the repair work should be made, from the arrangement of the dummy patterns 11A.
In order to identify a particular region for repair work, it is necessary to acquire the distribution of the dummy patterns 11A over a wide area, while search of such a wide area takes time, and the production cost of the semiconductor device is increased inevitably.
On the other hand, the foregoing Japanese Laid-Open Patent Application 9-306910 describes the technology enabling identification of the desired location of repair work, by dummy patterns represented as “A” or “B” in FIG. 4, regularly in the arrangement of the dummy patterns 11A for the purpose of mark. The dummy pattern that can be used for such a purpose of the mark can be formed by changing the shape or material thereof with regard to those of other dummy patterns.
In the case of identifying the location of the repair work based on the regularly repeated dummy patterns as shown in FIG. 4, it is true that the identification of location of the repair work can be made easily and quickly in the case the site of the repair work is located in the vicinity of the intersection of the array of the dummy patterns A repeated in the vertical direction and the array of the dummy patterns B repeated in the horizontal direction, while in the case the desired site of repair work is located in the area remote from such an intersection, it becomes necessary to search the intersection over a wide area, and the same situation explained with reference to FIG. 3 arises.
Further, when such arrays of dummy patterns A and B are formed on the substrate in large number for avoiding such a problem, the difficulty of locating the site of repair work cannot be avoided, as long as these arrays are formed regularly with a predetermined interval. Further, there is no guarantee that such dummy patterns A or B used for the mark can be formed repeatedly and regularly on a substrate.
(Reference 1) Japanese Laid-Open Patent Application 9-306910